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Ilia Polian
On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications
Conventional test methods for integrated circuits are increasingly unable to provide acceptable product quality. A possible remedy is to use improved models of manufacturing defects, or non-standard fault models. Consequently, the first part of the thesis focuses on the modeling of bridging faults. This includes resistive faults, which reflect the realities of nanoscale technologies. Although a continuum of defects are considered and non-trivial electrical interactions are accounted for, efficient discrete simulation algorithms are presented. Some of the proposed models are optimized for industrial application; the complex resistive models are currently being integrated into the tools of a leading design automation software maker. The second part of the thesis describes design-for-testability methods for dynamic defects: a multiple scan chain design approach and a self-test architecture. Two appendices deal with the relation of non-standard fault models to conventional stuck-at faults and their application for formal verification.
it – Information Technology (vormals it+ti), Oldenbourg Wissenschaftsverlag
Print ISSN: 1611-2776
Volume: 47, 03/2005
Pages: 172 - 174