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Michael Payer

Industrial Experience with Formal Verification

In recent years, Formal Verification has become an increasingly popular method to verify the functional equivalence of different design views. Just recently, designers also start to speak about Model Checking, a methodology that allows to analyze functional properties of a design. In the past both, equivalence checking and property checking, have been carried out with functional simulation; with today′s designs of several 100K or even Mio. gates this is not feasible anymore. The main reasons are the unsatisfactory runtime and the low coverage of this approach. In this paper, I will report experiences with Formal Equivalence Verification in an industrial design environment.

it – Information Technology (vormals it+ti), Oldenbourg Wissenschaftsverlag

Print ISSN: 1611-2776
Volume: 43, 01/2001
Pages: 16

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