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Jörg Bormann, Christoph Spalinger

Formal Verification for Non-Formalists

The property checker gateprop will be presented, which is the highlight of ten years of research and development on formal verification tools at the coroporate technology division of Siemens AG. Gateprop proves properties about the functionality of modules of 30 K to 100 K gates within few minutes. It has been successfully applied on telecommunication ASICs and on processor peripherals. At these examples the approach will be described that makes formal verification applicable to designers to allow the broad exploitation of its potential for quick and thourough functional verification.

it – Information Technology (vormals it+ti), Oldenbourg Wissenschaftsverlag

Print ISSN: 1611-2776
Volume: 43, 01/2001
Pages: 22

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