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Tom Bienmüller, Werner Damm, Jochen Klose, Hartmut Wittke

Formal Analysis and Verification of Statemate Designs

This article introduces the Statemate verification environment and demonstrates its applicability for the verification of embedded control units. We focus on newly added analysis techniques and the integration of Live Sequence Charts, an extension of Message Sequence Charts.

it – Information Technology (vormals it+ti), Oldenbourg Wissenschaftsverlag

Print ISSN: 1611-2776
Volume: 43, 01/2001
Pages: 29

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