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Stefan Pees, Andreas Hoffmann, Andreas Ropers, Heinrich Meyr

Fast Simulation of the TI-TMS320C54x DSP

In this paper a new technique for fast simulation of pipelined digital signal processors (DSPs) is presented. In contrast to the existing timed and untimed instruction set simulators which use the interpretive simulation technique, our simulator is based on the compiled simulation principle. Compared to interpretive simulators, the compiled technique enables simulation speedups of up to three orders of magnitude while keeping the same level of simulation accuracy. As a consequence, a much shorter turnaround time for development and verification of DSP software can be achieved. This paper presents an application of the compiled simulation technology on the MS320C54x DSP of Texas Instruments. Measurement results on real life examples show a speedup between 33 and 155 times compared to the currently available sim54x simulator of TI. For example, the simulation of an one-minute GSM pattern is reduced from three days to a single hour using the new SuperSim simulator.

it – Information Technology (vormals it+ti), Oldenbourg Wissenschaftsverlag

Print ISSN: 1611-2776
Volume: 41, 02/1999
Pages: 32

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