From an industrial point of view, equivalence checking is the most important formal verification technique being employed in today's design flows. Whereas conventional formal verification methods are based on binary decision diagrams and appropriate functional representations of the circuit, equivalence checking makes use of structural techniques. This paper reviews the basic ideas of current equivalence checking methods and explains how structural circuit properties can be exploited to drastically reduce the computational complexity of formal verification problems.
Print ISSN: 1611-2776
Volume: 43, 01/2001
Pages: 08