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Mirko Benz, Uwe Hatnik, Klaus Feske, Jürgen Haufe

Design Support for Hardware Based TCP/IP Accelerator

In this paper, we present an approach for hardware support of transport layer protocols on the basis of TCP/IP. We outline a hardware/software partitioning, a protocol engine for protocol processing acceleration and describe its transparent integration into standard systems. For the design, development and verification of such communication systems extensive simulation support is required. We describe how protocol engine VHDL models, a network simulator and existing networking applications were integrated to support this process. We present our approach for the simulation of communication systems and discuss the object structure and implementation details. To improve productivity we used a high level design methodology. The approach was validated with a FPGA based prototype for which we present first results.

it – Information Technology (vormals it+ti), Oldenbourg Wissenschaftsverlag

Print ISSN: 1611-2776
Volume: 44, 03/2002
Pages: 153

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