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Frank Vater, Peter Langendörfer

An Area Efficient Realisation of AES for Wireless Devices

Keywords: symmetric key cryptography, AES, hardware accelerator, wireless systems

In this paper we describe our own AES implementation, which supports encryption as well as decryption. Our major design goal was to reduce the area while still being capable to support high speed wireless networks such as IEEE 802.11a. Our AES solution provides a throughput of 54 MBit/s at 33 MHz and requires an area of 0.33 mm^2 in a 0.25 μm technology. This version may be run at up to 66 MHz which gives a throughput of 108 MBit/s. During the design we took into account global as well as local optimisations, i. e., optimisations which could be done inside an individual operation without affecting the rest of the design.

it – Information Technology (vormals it+ti), Oldenbourg Wissenschaftsverlag

Print ISSN: 1611-2776
Volume: 49, 03/2007
Pages: 188 - 193

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