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Andre Windisch, Thomas Schneider, Jochen Mades, Dieter Monjau, Manfred Glesner, Carsten Hammer, Wolfgang Ecker

A Flexible Simulation Environment for System-On-Chip Design

The design of heterogeneous systems-on-chip (SoC) is accomplished by a hierarchical composition of interacting subsystems. These subsystems are typically modeled in various domain-specific languages thus resulting in a multi-language system specification. This design approach differs from traditional design methods for homogeneous digital system, which are usually modeled in a single hardware description language on register transfer level. Therefore, the design of complex heterogeneous systems requires the development of new design tools. This article presents a newly developed design environment which supports simulation of multi-lingual system specifications in VHDL-AMS, Java, and C++.

it – Information Technology (vormals it+ti), Oldenbourg Wissenschaftsverlag

Print ISSN: 1611-2776
Volume: 42, 05/2000
Pages: 43

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